The present invention relates to a power amplifier including an input terminal for coupling to an input signal source. The amplifier arrangement further includes a comparator, a first input terminal of which is coupled to the input terminal of the amplifier arrangement, an output terminal which is coupled to an input terminal of a digital buffer, a buffer output terminal of the digital buffer is coupled to an output terminal of the amplifier arrangement and to a second input terminal of the comparator.
Such a power amplifier is already known in the art, e.g. from the article “An IC for Linearizing RF Power Amplifiers using Envelope Elimination and Restoration”, by D. Su and W. McFarland, ISSCC 1998 Technical Digest, paper 3.6-2. Therein, in FIG. 2a, a circuit is shown wherein a comparator in series with a Class-D buffer and a lowpass filter is coupled to a resistive load, this circuit having a direct feedback from the output to the input of the system.
A drawback of such a circuit is that its operation is based on switch-capacitors, which obviously need to be clocked, as is clearly shown in FIG. 2b. The presence of such a high-frequency sampling clock however seriously increases the power consumption. This seriously hampers its use in especially xDSL systems, where the power consumption of the output amplifier, is a serious issue.